The object of this work is to develop and demonstrate a pixel detector based on three-dimensional integration of sensor and readout electronics. Development of this technology will allow production of pixel sensors which are thin (<50 microns), have excellent and well controlled charge collection using fully depleted devices, and can use full CMOS readout without parasitic charge collection. These detectors will also be radiation hard. Such a device can be used as part of the vertex or forward detector for any of the detector concepts.
SOI is based on a thin "device wafer" with CMOS circuitry processed on a thicker "handle wafer", which is normally passive. In this work we will explore using a high resitivity handle wafer as a detector with vias between the device and detector layers. The detector diode is formed in the handle wafer as part of the topside processing.
The initial phase (~1 year) of the SOI work will concentrate on the type (float zone, epitaxial, or Cz material) and model the processing, of the handle wafer, including wafer thinning and backside contact fabrication. CMOS processing will be in 0.18 or 0.13 micron technology. If successful this will be followed by a ~9 mm square pixel device with test structures and prototype pixel readout. This phase will require full custom processing of a batch of 200 mm SOI wafers.